Irreducible : Basics Understanding of I2C Communication Protocol

Execution

Roles

  • Client - controller to manage communication
    • Action « Initiate communication on I2C bus, generate clock signal, send commands
    • Property « Multiple controller bus configurable
  • Server - target for the communication
    • Action « Listens for address on the bus and communicate only when addressed by controller
    • Property « Multiple target bus configurable
  • In essence, the controller manage communication flow, while the target responds wit the request data or perform the commanded action

Wire Communication

  • Serial Clock Line (SCL) - used in synchronization
    • Components
      1. Clock Signal (define controller timing
      2. Synchronization (align data transfer using clock)
  • Serial Data Line (SDL) - used in data transfer
    • Components
      1. Bidirectional Line
      2. Data Transfer (in sync with clock pulses on SCL)

Addressing and Data Transmission

  • A bus should have multiple unique address capacity that ensures a specific communication with an intended target

  • Most common address size are at 7-bits / 10-bits

  • The address frame concludes with a single bit that indicates whether the controller intends to write data to or read data from the target (0/1)

  • The Data Transmission compose of package of which our 1 byte (8-bits) of data is being transmitted.

  • The Data Transmission Package should compose of a start bit | address-bits |Ｒ/W bit | ACK | 8-bit Data Frame| ACK| Stop, where ACK denote acknowledgment of the recognition on address and on data of which the address is going to transfer

Transmission Steps

  • Step 1: The controller device initiates communication by generating a start condition on the bus. This is achieved by pulling the SDA line low while the SCL line remains high, followed by pulling the SCL line low.

  • Step 2: The controller transmits the 7-bit address of the specific target device it wants to communicate with. This is followed by an additional Read/Write (R/W) bit. The R/W bit indicates whether the controller intends to read data from (1) or write data to (0) the addressed target.

  • Step 3: Each target device on the bus continuously compares the transmitted address with its own. If the address matches, the addressed target device sends an ACK bit by pulling the SDA line low during the ninth clock pulse. If no target acknowledges (NACK), the controller may retry the transmission.

  • Step 4: Depending on the R/W bit, the controller either transmits an 8-bit data frame to the target (write operation) or receives an 8-bit data frame from the target (read operation).

  • Step 5: After receiving a data frame, the addressed target device sends an ACK bit to confirm successful reception. If there’s an error or the target cannot accept the data, it sends a NACK bit.

  • Step 6: The controller concludes the transmission by generating a stop condition. This involves pulling the SCL line high while the SDA line is still low, followed by pulling the SDA line high

Supplementary

  1. I2C Communication.pdf